1. Field of the Invention
The invention relates to electronic packaging, and particularly to such packaging which utilizes at least two different levels of conductive layers, e.g., signal, power and/or ground, as part thereof. Such packages are particularly adapted for use in information handling systems (computers).
2. Description of the Related Art
Typical electronic packages of the type described above include a dielectric substrate as a critical element thereof this substrate, e.g., of ceramic or a suitable polymer material such as fiberglass-reinforced epoxy resin (FR4), having the various desired conductive layers located thereon and/or therein.
Examples of various electronic packages of the type referred to herein are also described in the following identified US Letters Patents:
U.S. Pat. No. 4,430,365xe2x80x94Schaible et al.
U.S. Pat. No. 4,446,477xe2x80x94Currie et al.
U.S. Pat. No. 4,805,683xe2x80x94Magdo et al.
U.S. Pat. No. 4,835,593xe2x80x94Arnold et al.
Further attention is also directed to the following International Business Machines (IBM) Corporation Technical Disclosure Bulletins (TDBs) for descriptions of various ceramic substrates having circuitry thereon:
IBM TDB Vol. 22, No, 10, March, 1980
IBM TDB Vol. 32, No. 10A, March, 1990
In one known process for manufacturing an MCP package, which will include at least one chip electrically coupled to the circuitry thereof, the process begins with the deposition of a first layer of metal on the ceramic""s top surface. This layer is initially comprised of chromium-copper-chromium (Crxe2x80x94Cuxe2x80x94Cr) and is sputter deposited using known sputtering techniques. A layer of photoresist is then used to cover the Crxe2x80x94Cuxe2x80x94Cr layer, this layer then subjected to a series of photolithography steps (soft bake, expose, develop and bake) to form a desired pattern of such resist on the Crxe2x80x94Cuxe2x80x94Cr. Areas of unprotected metal in the underlying Crxe2x80x94Cxe2x80x94Cr layer are then removed using a known etching operation. The remaining protective pattern of resist is then removed (stripped) to expose the desired circuit pattern remaining on the ceramic""s top surface. This pattern, understandably, includes at least one and preferably several contact locations, each of which is adapted for being electrically coupled to a respective contact site on the chip(s). In the next step in the operation, a layer of dielectric, e.g., polyimide, is then deposited over the entirety of the remaining circuit pattern, including the contact locations, such deposition referred to in the industry as blanket coating (meaning to cover the entire circuitry).
Another series of photolithography steps are performed on the polyimide to define a pattern of openings (which are referred to as xe2x80x9cviasxe2x80x9d), selected portions (those which have been developed) of the dielectric polyimide then being removed to thereby expose parts of the circuitry thereunder. Understandably, the aforementioned contact locations are so exposed. At this point, the polyimide is baked and raised to a high cure state. In an alternative operation, laser ablation may be used instead of the chemical processing which forms part of the described photolithography steps to effect the desired selective removal of polyimide. The top layer of chromium of the Crxe2x80x94Cuxe2x80x94Cr layer is then removed using a known etching operation, such that the remaining exposed parts of the layer (the contact locations) are comprised of an upper portion of copper and a minute layer of chromium (which promotes adhesion of the copper-chromium to the ceramic).
In the next step of this manufacturing operation, a second layer of metal is deposited over the polyimide and the exposed conductive contact locations. A procedure known as a batch evaporation process is used, the result being that a layer comprised of chromium-copper-chromium is again formed. The aforementioned batch evaporation process is used at this stage rather than the described sputtering step because such a process has a prolonged heat cycle that serves to drive off solvents and water vapor which might remain and possibly interfere with the resulting interconnections between conductive layers. The previously described photolithography and wet processing steps are then repeated to define a second desired pattern for the second conductive layer. Final photolithography patterning followed by top chromium etch is then performed to selectively remove the chromium originally found in the top conductive layer. As in the case of the underlying first conductive layer, this second conductive layer will include at least one and preferably several contact locations for providing chip coupling.
The result of the above process is the formation of at least two conductive layers on the upper surface of the dielectric ceramic, each of these layers with at least one contact location thereon which is adapted for being electrically coupled, e.g., using solder as mentioned above, to respective contact sites on a chip which is then to be located over the exposed contact locations and coupled thereto. As further understood, these conductive layers are also separated by the dielectric layer of polyimide, which serves to electrically insulate the two as is necessary for successful operation of the package.
At least two disadvantages are associated with the above-described manufacturing process. One is that this process requires the performance of several diverse steps, requiring relatively large periods of time and the use of elaborate and expensive equipment. A second is that the process requires the formation of metal-to-metal interconnections at selected locations (those contact locations of the first layer with metal from the second conductive layer). Such interconnections are susceptible to variations in electrical resistance, which is of course highly undesirable in the manufacture of such precision-demanding products as multileveled electronic packages. To assure reliability between such interconnections to the levels demanded in this industry, special control measure and test operations are essential. This also adds to the overall costs of the final packages.
As will be described herein, the present invention describes a process for making a multilevel electronic package wherein at least two conductive layers are used, each with individual contact locations for being electrically coupled to respective contact sites on a semiconductor chip. Significantly, the contact locations of one layer are located at a greater distance (elevation) above the dielectric substrate""s upper surface while still being directly electrically coupled to the respective chip contact sites. As will be further described herein, the process for manufacturing such a product is capable of being performed with fewer steps and in less time than the aforementioned process for the MCP product described above. Equally significant, this process results in a product wherein metal-to-metal interconnections between separate metal conductor levels are unnecessary, thereby overcoming the above-mentioned disadvantages associated therewith. Although the present invention is particularly adapted for the manufacture of MCP products, this is not meant to limit the invention in that the process as defined herein may be readily adapted for utilization with other types of substrate packages, including those which use known FR4 and other dielectric materials for the base substrate member.
It is believed that such an electronic package and process for manufacturing same would represent a significant advancement in the art.
It is, therefore, an object of the present invention to enhance the art of electronic packages, including the processes used in this art to produce such multilevel electric packages.
It is another object of the invention to provide an electronic package which includes at least two individual conductive layers, each with respective contact locations, wherein the locations of each layer are located at a different distance from the underlying substrate""s upper surface while still providing direct electrical connection to the respective contact sites on a semiconductor chip when the chip is positioned on the substrate to form part thereof.
It is yet another object of the invention to provide a process for making such an electronic package.
It is still another object of the invention to provide such a process and resulting package structure which can be produced using fewer operational steps than that as described heretofore, as well as in less time, thereby representing a cost advantage to the ultimate consumer of the package as well as to those who produce it.
In accordance with one aspect of the invention, there is provided a method for making a circuitized substrate which comprises the steps of providing a substrate having a first surface, providing a circuit pattern on this first surface which will include at least one contact location, covering the first circuit pattern with dielectric material, providing a second circuit pattern on the dielectric which will also include its own contact location which is located at a different level from the contact location(s) of the first pattern, and then removing a portion of the dielectric layer to expose the contact location of the first layer. Both contact locations, being at different levels (distances from the substrate""s upper surface), are, significantly, adapted for being directly electrically connected, e.g., soldered, to respective sites on a semiconductor chip when the chip is positioned on the substrate.
In accordance with another aspect of the invention, there is provided a circuitized substrate which comprises a dielectric substrate having an upper surface, a first circuit pattern on the surface and including a first exposed contact location located a first distance from the surface, a layer of dielectric on the first pattern and including an opening therein to provide exposure for the first contact location, and a second circuit pattern on the dielectric and including a second contact location located at a second, greater distance from the surface than the first contact location of the first pattern. This second contact location is also exposed, with both exposed first and second contact locations adapted for being directly electrically coupled to the respective contact sites on a semiconductor chip.
In accordance with yet another aspect of the invention, a method is described for making a multilevel electronic package. The method comprises applying a conductive layer onto a surface of a substrate, the conductive layer having an exposed top surface. A layer of an organic dielectric is applied over the exposed top surface of the first conductive layer and is cured. A second conductive layer is formed on the cured dielectric layer at a greater distance from the surface of the substrate than the first conductive layer. At least a portion of the second conductive layer is removed to expose the dielectric layer immediately therebeneath, and the exposed dielectric layer is removed to expose a portion of the first conductive layer. One or more solder connections is formed on the exposed portion of the first conductive layer, and one or more solder connections is formed on the second conductive layer, there being no interconnection between the solder connections on the first layer and the solder connections on the second layer to form a subassembly. The solder connections on the first conduct layer of the first conductive layer and the solder connections on the second conductive layer can then be mated to a semiconductor chip, a metal clip or other electronic subassembly.